The time elapsed from the application of an ideal step input to the time at which the system output has entered and remained within a specified error band.

为了提高系统的响应速度，我们需要尽可能缩短控制器的建立时间。

The minimum amount of time a data signal must be held stable before the occurrence of a clock edge in a digital circuit.

如果数据信号不满足建立时间的要求，触发器可能会出现亚稳态。